From c5b1ff0b9414bffaa77b166b70e631a76b2d5d48 Mon Sep 17 00:00:00 2001
From: unhappy-ending <85425531+unhappy-ending@users.noreply.github.com>
Date: Thu, 16 May 2024 23:31:12 -0400
Subject: [PATCH] Update Makefile to use $(CC) rather than cc

Calling cc directly causes a build failure on Clang/LLVM based Gentoo
machines that use LLVM specific toolchain flags.
---
 src/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/Makefile b/src/Makefile
index d473953..5c3efc7 100644
--- a/src/Makefile
+++ b/src/Makefile
@@ -66,7 +66,7 @@ $(DEPFILES):
 include $(wildcard $(DEPFILES))
 
 $(TARGET): $(OBJS)
-	cc -o $(TARGET) $(OBJS) ${LDFLAGS}
+	$(CC) -o $(TARGET) $(OBJS) ${LDFLAGS}
 
 ifeq ($(PREFIX),)
   PREFIX := /usr/local