57 lines
2.1 KiB
Rust
57 lines
2.1 KiB
Rust
// SPDX-License-Identifier: Apache-2.0 OR MIT
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/*
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Refs:
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- Xtensa Instruction Set Architecture (ISA) Summary for all Xtensa LX Processors
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https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/silicon-solutions/compute-ip/isa-summary.pdf
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- Linux kernel's Xtensa atomic implementation
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https://github.com/torvalds/linux/blob/v6.13/arch/xtensa/include/asm/atomic.h
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*/
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use core::arch::asm;
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pub(super) use core::sync::atomic;
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pub(super) type State = u32;
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/// Disables interrupts and returns the previous interrupt state.
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#[inline(always)]
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pub(super) fn disable() -> State {
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let ps: State;
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// SAFETY: reading the PS special register and disabling all interrupts is safe.
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// (see module-level comments of interrupt/mod.rs on the safety of using privileged instructions)
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unsafe {
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// Do not use `nomem` and `readonly` because prevent subsequent memory accesses from being reordered before interrupts are disabled.
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// Interrupt level 15 to disable all interrupts.
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// SYNC after RSIL is not required.
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asm!(
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"rsil {ps}, 15", // ps = PS; PS.INTLEVEL = 15
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ps = out(reg) ps,
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options(nostack),
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);
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}
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ps
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}
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/// Restores the previous interrupt state.
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///
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/// # Safety
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///
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/// The state must be the one retrieved by the previous `disable`.
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#[inline(always)]
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pub(super) unsafe fn restore(prev_ps: State) {
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// SAFETY: the caller must guarantee that the state was retrieved by the previous `disable`,
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// and we've checked that interrupts were enabled before disabling interrupts.
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unsafe {
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// Do not use `nomem` and `readonly` because prevent preceding memory accesses from being reordered after interrupts are enabled.
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// SYNC after WSR is required to guarantee that subsequent RSIL read the written value.
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// See also 3.8.10 Processor Control Instructions of Xtensa Instruction Set Architecture (ISA) Summary for all Xtensa LX Processors.
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asm!(
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"wsr.ps {prev_ps}", // PS = prev_ps
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"rsync", // wait
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prev_ps = in(reg) prev_ps,
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options(nostack),
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);
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}
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}
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