Update Makefile to use $(CC) rather than cc

Calling cc directly causes a build failure on Clang/LLVM based Gentoo
machines that use LLVM specific toolchain flags.

src/Makefile

@@ -66,7 +66,7 @@ $(DEPFILES):
 include $(wildcard $(DEPFILES))
 
 $(TARGET): $(OBJS)
-	cc -o $(TARGET) $(OBJS) ${LDFLAGS}
+	$(CC) -o $(TARGET) $(OBJS) ${LDFLAGS}
 
 ifeq ($(PREFIX),)
   PREFIX := /usr/local