Update Makefile to use $(CC) rather than cc
Calling cc directly causes a build failure on Clang/LLVM based Gentoo machines that use LLVM specific toolchain flags.
This commit is contained in:
committed by
Geoffrey D. Bennett
parent
955dd1355a
commit
c5b1ff0b94
@@ -66,7 +66,7 @@ $(DEPFILES):
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include $(wildcard $(DEPFILES))
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include $(wildcard $(DEPFILES))
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$(TARGET): $(OBJS)
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$(TARGET): $(OBJS)
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cc -o $(TARGET) $(OBJS) ${LDFLAGS}
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$(CC) -o $(TARGET) $(OBJS) ${LDFLAGS}
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ifeq ($(PREFIX),)
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ifeq ($(PREFIX),)
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PREFIX := /usr/local
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PREFIX := /usr/local
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